Artificial Intelligence and Machine Learning in Chip Design

Explore innovative AI/ML applications in EDA, enhancing speed, efficiency & cost while preparing for the future of semiconductor innovation.

  • 0.4 CEU / 4 PDH credits
  • Launched 2024
  • 2 courses
  • 4 hours

Course Description

Artificial intelligence (AI) and machine learning (ML) techniques are being rapidly introduced into modern chip design methodologies and the underlying electronic design automation (EDA) tools. This offers integrated-circuit (IC) chip companies and their engineers the potential to improve product quality in key dimensions – speed, energy efficiency, and cost – with less engineering resources and faster time-to-market. Understanding these technical advances and their potential applications can help engineers improve their design methods while preparing for the coming fundamental shifts in how chip design is performed. This course series will provide broad coverage of what engineers need to know about AI and ML in chip design and EDA: why AI and ML technologies are the future; high-value applications in chip design and design automation; the AI and ML technologies most relevant to chip design; infrastructure and deployment considerations; and what lies ahead.

Brought to you by IEEE Educational Activities in partnership with IEEE Future Directions and IEEE Global Semiconductors.

Course Objectives

  • Essential knowledge to leverage AI and ML effectively in chip design and EDA
  • Understanding of the rationale behind these technological shifts to identifying high-value applications and selecting relevant AI and ML technologies
  • Insights into optimizing design methods and preparing for the future of chip design

Authors and Instructors

Andrew B. Kahng

Distinguished Professor of CSE and ECE and holder of the endowed chair in high-performance computing at the University of California at San Diego

Andrew B. Kahng is Distinguished Professor of CSE and ECE and holder of the endowed chair in high-performance computing at the University of California at San Diego. He received the A.B. degree in applied mathematics (physics) from Harvard College, and the M.S. and Ph.D. degrees in computer science from UC San Diego. From 1989 to 2000, he was on the UCLA computer science faculty before moving to UC San Diego in 2001. He was visiting scientist at Cadence Design Systems (1995-97) and founder/CTO at Blaze DFM (2004-06). He is coauthor of 3 books and over 500 journal and conference papers, holds 35 issued U.S. patents, and is a Fellow of IEEE and of ACM. He was the 2019 Ho-Am Prize laureate in Engineering. From 2000-2016 he served as international chair/co-chair of the International Technology Roadmap for Semiconductors (ITRS) Design and System Drivers working groups. He has served as general chair of IEEE-sponsored conferences such as the Design Automation Conference, the International Symposium on Physical Design, and the Workshop on Machine Learning. He has also served on the editorial boards of IEEE Transactions on VLSI, IEEE Transactions on Circuits and Systems I, and IEEE Design and Test (where he contributes the regular column, “The Road Ahead”).

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